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Integrated power devices

Modeling and characterization of the hot-carrier stress degradation in Smart Power MOSFETs

One of the key challenges in building power devices for next generation Smart-Power technology is their reliability. In this research activity the high-voltage devices will be studied with respect to their major electrical characteristics, namely, specific on-resistance versus breakdown voltage and safe operating area before and after hot carrier stress. Extensive numerical investigations will be carried out with the aim of clarifying the most relevant physical effects up to high drain and gate biases. The major goal of this activity is the development of a predictive TCAD tool for HCS degradation.


Package Influences on High-Voltage Semiconductor FETs

The current trend towards increasing the integration of high-voltage devices and low-voltage circuits within one package to realize compact power systems and/or increase operation frequency drives new configurations (e.g. stacked dies) for which no reliability study has been published yet. Little analysis has been reported on the physical mechanisms, material features and design aspects that drive them. The proposed research activity deals with the effect of charging and polarization of molding compounds and other packaging materials, experimental characterization of losses and model validation. The expected outcome of the research activity is an extensive overview of package-to-die coupling effects versus modeled material properties, die technology and package designs.


Investigation of Reliability Issues and Physical Mechanisms of Breakdown in High-Voltage GaN/AlGaN HFETs on Silicon Substrates

This project focuses on the investigation of reliability issues and achievable performance of GaN-HFETs grown on Si substrates for power conversion applications as replacement for Si-based MOSFETs. TCAD device simulations, physical modeling and reliability investigations will be extensively addressed. The simulation decks of power GaN FETs on silicon substrate will be set up by accounting for different stacks of materials. The main goal will be the determination and comparison of performance stability and robustness of GaN devices for different geometries, by varying the interface trap configurations and the operating temperatures.